Job Description

Candidate is responsible for performing validation of reliability ESD and LU design rules and PERC-Sch and PERC-LDL checks across multiple process technology and related tools and flows. Candidate is also responsible for developing QA methodology, define and develop required automations. Drive innovation and initiatives to enhance existing automation, tools and methodology. Identify and analyze problems, plans, tasks and solutions. Candidate is expected to engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification. Test-cases creation for debugging and validation. Candidate should have ability to work in a dynamic and team oriented environment. Works with EDA vendors on tool improvements to enhance performance and add functionality. Develops automation of QA flow methodologies for specific technology nodes to scale up QA coverage. Documents and monitors QA results. Candidate should be creative, independent and out of the box thinker with strong problem solving skills and analytical ability. Candidate should have attention to details, strong organization skills. Candidate should have excellent written and verbal communication skills to present complex issues with clarity to drive decisions.

Qualifications

Master's in EC or EE or CSE with 10+ yrs Exp or Bachelor's in EC or EE or CSE with 12+yrs Exp. Working knowledge of Cadence Voltus-Fi, Synopsys CSRA, ANSYS Totem, or ANSYS Pathfinder, PERC (Siemens, Synopsys, Cadence). Familiarity with semiconductor reliability physics and failure mechanisms, including electro-migration, latch-up, and electrostatic discharge (ESD). Custom circuit simulation, layout editing, layout verification, and RC extraction. Experience working on 7nm or lower process nodes desired. Must have knowledge of Programming/scripting in Unix shell, Perl, Python, Ruby, Tcl, C++, or equivalent. Desire to grow in the reliability verification career path is preferred.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.